Please note: At the current time, the VHDL translator is no longer being
maintained or enhanced.
Once Veritak supports a significant subset of system-verilog, a re-written
translator will be made available as Open Source as well as SV parser written
For our customers located in China, please contact our Chinese distributor
About the Author
Veritak is developed by one person, Tak.Sugawara.
"Tak" as he likes to be called was born in beautiful city in Japan. He used to
be a hardware design engineer in the field of Disk Controllers. He has designed
over 30 ASICS, with a cumulative volume of over 10 million units delivered
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