Verilog HDL Simulator Veritak


To purchase Veritak, please see our how to Purchase page.


For customers and prospects located in China, please contact our Chinese distributor.  


Please note: At the current time, the VHDL translator is no longer being maintained or enhanced. Once Veritak supports a significant subset of system-verilog, a re-written translator will be made available as Open Source as well as SV parser written with C++.
For our customers located in China, please contact our Chinese distributor.

About the Author

Veritak is developed by one person, Tak.Sugawara. "Tak" as he likes to be called was born in beautiful city in Japan. He used to be a hardware design engineer in the field of Disk Controllers. He has designed over 30 ASICS, with a cumulative volume of over 10 million units delivered worldwide

Open Sources
For questions about purchasing Veritak or general inquiries
For technical questions from registered users
We normally respond to support requests within 2 business days.

If you know you are experiencing a Veritak problem, and not your own problem, please attach a small code sample that reproduces the problem. We know this is the fastest way to find a solution to the problem.

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