Coregen
Let's make my_rom.v, 16x4096words RAM with initialized data using coregen.
(coregenlib is not attached in WEBPACK.)

Set initial file as "modulator.coe"

RTL Project
When project file and generate file(my_rom.v) is not on the same folder, you must use Add InludeDir for the folder where generated file exist as below See Project Setting for library compilaration..

Load Project "RTL_coregenrom.vtakprj".
Test bench ("coregen_rom_test.v") reads ram data incrementally and decrementally, 6cbc,70c3....

Here is description of "modulator.coe"

Gate Simulation Project
This is combined project with DCM.
See DCM.