5 Project Options


5.1 Waveform
5.1.1 Select Waveform

Supported. The operation is the same as Veritak. Please see veritak tutorial.

5.1.2 $dumpon/$dumpoff

This is new feature. You can control on /off state of VeritakSV's waveform processing by source level.
To enable this, you should check following boxes on project setting.


Apply $dumpon/$dumpoff/$dumpclear for waveforms
Save all sim data.



Here is an example.

initial begin

    repeat(100) begin
        #1000000;
        $dumpoff;//mark x on all of waveforms and disable waveform operation
        $display("dumpoff=%t",$time);
        #1000000;
        $dumpon;//enable all waveform operation
        $display("dupon=%t",$time);
    end

end

Note all waveforms become x while $dumpoff. So, this saves memory consumption for waveforms. You can check the consumption for waveform by the bottom bar "DispDisk= xx MB". When $dumpoff is enabled, DispDisk value should not be increased.




5.1.3 $dumpclear

It behaviors as $dumpoff at time0 on anytime.

For extremely long simulations,if you do not want to use a lot of memory , but you want to see the waveforms when some triggering signal (the error) becomes active,this is it.
$dumpclear clears all histories of waveforms, forgets everything (means all waveforms become x), but gets free memory instead.

initial begin

   repeat(100) begin
      #1000000;
      $dumpoff;//mark x on all of waveforms and disable waveform operation
      $display("dumpoff=%t",$time);
      #1000000;
      $dumpon;//enable all waveform operation
      $display("dupon=%t",$time);
   end
end

reg err=0;

task do_some_test;

      #3700000;//Time must be consumed for each $dumpon/$dumpoff/$dumpclear
      err=$random;
      $display("err=%b",err);

endtask

initial begin

        repeat(10000000) begin
            $dumpon();
            do_some_test();
            if (!err) $dumpclear();//It means all of waveform histories are cleared.
            #1;//Time must be consumed for each $dumpon/$dumpoff/$dumpclear
        end
end

5.2 State Save

Currently it saves entire simulator state to StateSave file just After compilation There are several restrictions below.

• The function is available only in SV6464(64bit OS and 64bit simulator)
• Simulator version has its own statesave, in other words, You can not load other versions statesave-file.
• Only available for Verilog 2001 syntax modules. (SV modules are not supported yet.)

When is this feature useful?


You have long compile time and need to do some regression tests for slightly different parameters, then this feature should be useful. Because loading time is far less than compile time per each test. Slightly different parameters can be used by using $test$plusargs /$value$plusargs system tasks. Please note available parameters that can be changed as invoked parameters are only XX$plusargs , other parameters, such as -Define etc.. can not be changed. This is true for the options for compiler ,such as Save All Sim Data..However,Inculde path can be referred in run time, so they should be specified in the project as original project.

Another advantage of using state-file is reduction of compile-time memory. For example, memory footprint becomes 2.4GB after loading statesave-file whereas 3.6GB was necessary for compilation and runtime. Loading Time is 2sec whereas compile time is 2min.

1) Make State Save Project

Check After compilation and Make Load Project in your project as below. Save and Load it.


After Compilation, you should see Saving... in compiler pane.


2) Load the project

State save file's project is made in the same folder as "Load_ + project_name + _version".vtakprj.

Load the project. Loading time is around 1-2 sec in nominal situation.

5.3 VCD Comparison
5.3.1 Veritak-VCD comparison

You can compare Veritak waveform and VCD waveform by clicking　menu->utility->entier waveform comparison.
Please note at least one (empty) waveform should be displayed when this feature is enabled ,and checking "check by red Marker" in dialog
by clicking ->menu->utility->Add VCD Start Time Offset.



5.3.2 VCD- VCD comparison
　　You can compare VCD-VCD files.as described above as well. In addition you can use command line as below.
　　　
　　　VeritakWin.exe file1.vcd file2.vcd

　　　An example of Batch file is shown in Commands/vcd_comparison. In command line, if there is no difference between 2 VCD files, VeritakWin returns immediately, but if there is a difference between 2 VCD file, VeritakWin displays different signals by showing red mark by time order as above automatically.