Single Source

If single VHDL , do Drag & Drop to Veritak icon . Translation Examples are found at http://www.sugawara-systems.com/open_sources.htm

This process will generate one single file "translated..v" as successful translation result. 

It is necessary to make VHDL project like verilog project.
It is not easy task to translate VHDL to Verilog because semantics difference between VHDL and Verilog HDL is so big especially in behavior statement. Test bench translation will be almost impossible. Even in RTL sources, most cases of translation may require user intervention.

Procedure:

• Make new project. VHDL->Verilog Translator => New Project
• Add  VHDL files to translate
• Execute Translate. Translator scans VHDL sources.. If no error is detected in VHDL sources, then translation process will begin. This process will generate one single file "project_name.v" as successful translation result. 
• Compile "project_name.v" as verilog single source.
• If Verilog compilation error occurs , modify the source manually.
• Check simulation result.
• Translation result is sometimes not suitable for synthesis or other simulators.(Veritak Simulator uses extensions.) In that case, additional manual translation will be required.

Notes;

• $conv.. option enables generation of $conv.. system function(Veritak Special) in translated source.
• Generate vhdl_file_name.v option enables generation of "vhdl_file_name.v" instead of "project_name.v"

Here is a link to project for translating plasma (Most Mips I in opencores project.)