5.1.4 Memory with initialized value

Af first,make memory initialization file by Using Quartas2.
Menu New->File

This is an example.
Memory words = 1024 ,and bit width of word =32bits

Memory pattern is incremental here in example.

Save Mif file as Hex. (Since Veritak can not read mif file directly, we use HEX file, which should be converted to verilog file by altera_mf.v.)

Set appropriate bit width and words in MegaWizard.

Set HEX file(generated by above operation) as memory initialization file.

That's all.!

Simulation by RTL (altera\sram_initialize_HEX)

Simulation by Gate (altera\sram_initialize_HEX\simulation\custom)

<MIF FILE>
Set "NO_PLI" in a project as follows. Th sample project is located in altera\sram_initialize_MIF folder.

5.1.5MegaWizard Generated IP's simulation

You can simulate WegaWizard generated gate-level simulation model. The generated extension is .vo.

( The gate level models are generated by checking "Generate Simulation Model " in MegaWizard as well as simple test bench.)

The following is an example of project by using SratixⅢ for DDR3 controller.

Add generated module in the folder of testbench.
Add Lib Dir for the folder which has many generated module files.
Add Altera primitive libraries. （Required libraries are displayed in MegaWizard.）
Add all *.vo files.

TIPS:

A Disk may be easily full because generated netlist are huge. You can increase archive size from default setting of 400MB, for example, to 10GB, but may be more preferred to use selective save or VCD from the viewpoint of simulation speed.
As for PCIExpress, the core is too huge to compile and run at the same time for 32 bit environment, it is recommended to compile and run under 64bit OS environment. Another solution is to use save/restore function, compile the core ,and load and run the project separately.
You'll see "RunTime Error Attempted to Read beyond Array Index" in altera_mf.v. This is due to invalid index accessing in the library. Please check Suppress　R.T.warning, you don't like to see the message.