For convenience in tutorial , we assume following folder tree for installed package and FPGA library.
It is not necessary to copy related files in fpga vendor as below. but may be useful for running Veritak project without modification. (Install-package can not include them since they are property of FPGA vendors.) They are necessary on the same drive as veritak project.

In top down design, Test bench is basically common between RTL and gate simulation.RTL design is synthesized in FPGA vendor tools and generates synthesized results as

• *.vo (Altera) *_timesim.v (Xilinx) - synthesized results for simulation.
• *.sdo(Altera) *.sdf (Xilinx)  -timing files for back-annotation

Replacing RTL design to gate level , gate simulation can be performed. In this section we make Veritak project for gate simulation using the same test bench as RTL, and FPGA vendor library for both Xilinx and Altera.