Coregen

Let's make 150MHz clock from 50MHz clock.

RTL Simulation
Here is configuration of RTL project.
"my_dcm.v" is coregened file.

Load Project "RTL_coregen_dcm.vtakprj".
After Locked, dcm output appears as below. Cycle is 10n*2/3=6.667ns, while input clock's cycle is 20ns.

DCM & RAM Combined RTL Simulation

Here is combined source for synthesis.

Load Project "RTL_coregen_dcm_and_rom.vtakprj"

DCM & RAM Gate Simulation

Configuration of Project is as follows.

Load Project "Gate_coregen_dcm_and_ram.vtakprj".

You can observe DCM oscillates 150MHz (3clocks=20ns) after DCM locked.