Megawizard
Use Megawizard to generate pll module.

In this tutorial, we assume the pll has following spec.

• input frequency=16MHz
• output frequency x8=128MHz

RTL Simulation

8x locked signal(c0) can be observed with zero-delay after PLL locked.

Configuration of this project is as follows.
"altera_pll.v" is generated module by Megawizard.

Synthesis

Gate Simulation

In gate simulation, PLL output(c0) is 8x locked, however 2.062ns delay by input clock. is observed.

Configuration of project in gate simulation

Note on Altera/Xilinx Gate Level Simulation

Altera SDF/ Xilinx  ACTEL SDF  in Project Setting before Compilation must be checked for post layout simulation..

General Rule to select library

Please observe compiler complains. carefully.
For example, if compile error shows following line,

dffeas \altpll_component|auto_generated|pll_lock_sync

You know module "dffeas" is missing..
Searching the keyword "dffeas" in libraries, you will find proper library. In this case, you should add library "altera_primitives.v" having dffeas. to the project..