2. Design
2.1 Pipeline Consideration

If PC is incremental then YACC performs all instruction at 1 clock cycle including memory R/W. However, if PC is not incremental, Jump address calculation is necessary , which requires more cycles in YACC.

(1) Normal Commands :- 1Clock Cycle

Time Slot	Stage1	Stage2	Stage3	Stage4	Stage5
	Set Register File Address	Read Register File ALU_LEFT/Right Latch	Mem Write AReg<=ALU	Mem Read NReg<=AReg	Write Register File RReg<=NReg
1	Fetch & Decode
2	Fetch & Decode	ReadRegisterFile
3	Fetch & Decode	ReadRegisterFile	ALU
4		ReadRegisterFile	ALU	MEM
5			ALU	MEM	WB
6				MEM	WB
7					WB
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(2) Jump address is known at fetch Cycle -2 Clock Cycle

GCC tries to insert delayed branch command just after jump command. Therefore no performance penalty will be in most cases.

Time Slot	Stage1	Stage2	Stage3	Stage4	Stage5
	Set Register File Address	Read Register File ALU_LEFT/Right Latch	Mem Write AReg<=ALU	Mem Read NReg<=AReg	Write Register File RReg<=NReg
1	Fetch & Decode(Jump Detected)
2	Delayed Branch Command	Set Jump Address
3	Fetch & Decode(Jumped Address)	ReadRegisterFile
4		ReadRegisterFile	ALU
5			ALU	MEM
6				MEM	WB
7					WB
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(3) Register Jump : -3 Clock Cycle

Jump Address is not determined until Register File is read. This will result performance penalty.

Time Slot	Stage1	Stage2	Stage3	Stage4	Stage5
	Set Register File Address	Read Register File ALU_LEFT/Right Latch	Mem Write AReg<=ALU	Mem Read NReg<=AReg	Write Register File RReg<=NReg
1	Fetch & Decode(Register Jump Detected)
2	Delayed Branch Command	ReadRegisterFile
3	Fetch & Decode	ReadRegisterFile	Set Jump Address
4	Fetch & Decode(Jumped Address)	NOP	ALU
5		ReadRegisterFile	NOP	MEM
6			ALU	NOP	WB
7				MEM	NOP
8					WB

(4) Branch with Branch commands : -4 Clock Cycle

We can not set branch address until taken is set. This will be big penalty in YACC. To improve this situation, branch prediction mechanism will be necessary. (Not implemented in YACC).

Time Slot	Stage1	Stage2	Stage3	Stage4	Stage5
	Set Register File Address	Read Register File ALU_LEFT/Right Latch	Mem Write AReg<=ALU	Mem Read NReg<=AReg	Write Register File RReg<=NReg
1	Fetch & Decode(Branch command Detected)
2	Delayed Branch Command	ReadRegisterFile
3	Fetch & Decode	ReadRegisterFile	Set Not Taken
4	Fetch & Decode	NOP	ALU	Set Branch Address
5	Fetch & Decode(Branch Address)	NOP	NOP	MEM
6		ReadRegisterFile	NOP	NOP	WB
7			ALU	NOP	NOP
8				MEM	NOP

(5) Not Branch with Branch commands : -3 Clock Cycle

After Taken is Not set, we understand PC is incremental.

Time Slot	Stage1	Stage2	Stage3	Stage4	Stage5
	Set Register File Address	Read Register File ALU_LEFT/Right Latch	Mem Write AReg<=ALU	Mem Read NReg<=AReg	Write Register File RReg<=NReg
1	Fetch & Decode(Branch command Detected)
2	Delayed Branch Command	ReadRegisterFile
3	Fetch & Decode	ReadRegisterFile	Set Not Taken
4	Fetch & DecFetch (Not Branched Address)	NOP	ALU
5		ReadRegisterFile	NOP	MEM
6			ALU	NOP	WB
7				MEM	NOP
8					WB

(6) Interrupt -2 Clock Cycle

In YACC interrupt is like jump command.To simplify the interrupt logic,Interrupt is inhibited during mul/div/jump/branch commands in YACC implementation.

Time Slot	Stage1	Stage2	Stage3	Stage4	Stage5
	Set Register File Address	Read Register File ALU_LEFT/Right Latch	Mem Write AReg<=ALU	Mem Read NReg<=AReg	Write Register File RReg<=NReg
1	Fetch & Decode(Interrupt)
2	NOP	Set Interrupt Address/ Save Returned Address
3	Fetch & Decode(Interrupt Address)	NOP
4		ReadRegisterFile	NOP
5			ALU	NOP
6				MEM	NOP
7					WB
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