2.3 Supported Instructions
Not supported item is displayed as red characters.
Unaligned load and store operations (LWL,SWL,LWR,SWR) are not supported.
ADD -- Add
| Description:
| Adds two registers and stores the result in a register(Exception by Overflow)
|
| Operation:
| $d = $s + $t;
|
| Syntax:
| add $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5bit |
6'b100_000 |
|
ADDI -- Add immediate
| Description:
| Adds a register and a signed immediate value and stores the result in a
register
|
| Operation:
| $t = $s + imm;
|
| Syntax:
| addi $t, $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b001000 |
5bit |
5bit |
16bit |
|
ADDIU -- Add immediate unsigned
| Description:
| Adds a register and an unsigned immediate value and stores the result in a
register
|
| Operation:
| $t = $s + imm;
|
| Syntax:
| addiu $t, $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b001001 |
5bit |
5bit |
16bit |
|
ADDU -- Add unsigned
| Description:
| Adds two registers and stores the result in a register
|
| Operation:
| $d = $s + $t;
|
| Syntax:
| addu $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5'h0 |
6'b100_001 |
|
AND -- Bitwise and
| Description:
| Bitwise ands two registers and stores the result in a register
|
| Operation:
| $d = $s & $t;
|
| Syntax:
| and $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5'h0 |
6'b100100 |
|
ANDI -- Bitwise and immediate
| Description:
| Bitwise ands a register and an immediate value and stores the result in a
register
|
| Operation:
| $t = $s & imm;
|
| Syntax:
| andi $t, $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b001100 |
5bit |
5bit |
16bit |
|
BEQ -- Branch on equal
| Description:
| Branches if the two registers are equal
|
| Operation:
| if $s == $t PC +=imm << 2;
|
| Syntax:
| beq $s, $t, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b000100 |
5bit |
5'h0 |
16bit |
|
BGEZ -- Branch on greater than or equal to zero
| Description:
| Branches if the register is greater than or equal to zero
|
| Operation:
| if $s >= 0 PC +=offset << 2;
|
| Syntax:
| bgez $s, offset
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b000001 |
5bit |
5'b00001 |
16bit |
|
BGEZAL -- Branch on greater than or equal to zero and link
| Description:
| Branches if the register is greater than or equal to zero and saves the
return address in $31
|
| Operation:
| if $s >= 0 $31 = PC + 8 ; PC +=imm << 2;
|
| Syntax:
| bgezal $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b000001 |
5bit |
5'h10001 |
16bit |
|
BGTZ -- Branch on greater than zero
| Description:
| Branches if the register is greater than zero
|
| Operation:
| if $s > 0 PC +=imm << 2;
|
| Syntax:
| bgtz $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b000111 |
5bit |
5'h0 |
16bit |
|
BLEZ -- Branch on less than or equal to zero
| Description:
| Branches if the register is less than or equal to zero
|
| Operation:
| if $s <= 0 PC +=imm << 2;
|
| Syntax:
| blez $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b000110 |
5bit |
5'h0 |
16bit |
|
BLTZ -- Branch on less than zero
| Description:
| Branches if the register is less than zero
|
| Operation:
| if $s < 0 PC+=imm << 2;
|
| Syntax:
| bltz $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b00001 |
5bit |
5'b00000 |
16bit |
|
BLTZAL -- Branch on less than zero and link
| Description:
| Branches if the register is less than zero and saves the return address in
$31
|
| Operation:
| if $s < 0 $31 = PC + 8 ; PC+=imm << 2;
|
| Syntax:
| bltzal $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b000001 |
5bit |
5'b10000 |
16bit |
|
BNE -- Branch on not equal
| Description:
| Branches if the two registers are not equal
|
| Operation:
| if $s != $t PC+=imm << 2;
|
| Syntax:
| bne $s, $t, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b000101 |
5bit |
5'h0 |
16bit |
|
Break -- Break
| Description:
| Generates break point.
|
| Operation:
|
|
| Syntax:
| break
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
????? |
????? |
????? |
????? |
6'b001101 |
|
DIV -- Divide
| Description:
| Divides $s by $t and stores the quotient in $LO and the remainder in $HI
|
| Operation:
| $LO = $s / $t; $HI = $s % $t;
|
| Syntax:
| div $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5'h0 |
5'h0 |
6'b011010 |
|
DIVU -- Divide unsigned
| Description:
| Divides $s by $t and stores the quotient in $LO and the remainder in $HI
|
| Operation:
| $LO = $s / $t; $HI = $s % $t;
|
| Syntax:
| divu $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5'h0 |
5'h0 |
6'b011011 |
|
J -- Jump
| Description:
| Jumps to the calculated address
|
| Operation:
| PC = nPC; nPC = (PC & 0xf0000000) | (imm26 << 2);
|
| Syntax:
| j imm26
|
| Encoding:
|
| OPCODE |
Immediate |
| 6'b000010 |
26bit |
|
JAL -- Jump and link
| Description:
| Jumps to the calculated address and stores the return address in $31
|
| Operation:
| $31 = PC + 8 ; PC = nPC; nPC = (PC & 0xf0000000) | (imm26 <<
2);
|
| Syntax:
| jal imm26
|
| Encoding:
|
| OPCODE |
Immediate |
| 6'b000011 |
26bit |
|
JALR -- Jump and link Register
| Description:
| Jump to the address contained in register $s and stores the return address
in $d
|
| Operation:
| $d = PC + 8 ; PC = $s
|
| Syntax:
| jalr $d,$s
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5'h0 |
5bit |
5'h0 |
6'b001001 |
|
JR -- Jump register
| Description:
| Jump to the address contained in register $s
|
| Operation:
| PC = nPC; nPC = $s;
|
| Syntax:
| jr $s
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5'h0 |
5'h0 |
5'h0 |
6'b001000 |
|
LB -- Load byte
| Description:
| A signed extented byte is loaded into a register from the specified address.
|
| Operation:
| $t = MEM[$s + imm]; ;
|
| Syntax:
| lb $t, imm($s)
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b100000 |
5bit |
5bit |
16bit |
|
LBU -- Load byte unsigned
| Description:
| A unsigned extented byte is loaded into a register from the specified address.
|
| Operation:
| $t = MEM[$s + imm]; ;
|
| Syntax:
| lbu $t, imm($s)
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b100100 |
5bit |
5bit |
16bit |
|
LH -- Load Half
| Description:
| A signed extented half word is loaded into a register from the specified
address.
|
| Operation:
| $t = MEM[$s + imm]; ;
|
| Syntax:
| lh $t, imm($s)
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b100001 |
5bit |
5bit |
16bit |
|
LHU -- Load Half unsigned
| Description:
| A byte is loaded into a register from the specified address.
|
| Operation:
| $t = MEM[$s + imm]; ;
|
| Syntax:
| lhu $t, imm($s)
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b100101 |
5bit |
5bit |
16bit |
|
LUI -- Load upper immediate
| Description:
| The immediate value is shifted left 16 bits and stored in the register. The
lower 16 bits are zeroes.
|
| Operation:
| $t = (imm << 16);
|
| Syntax:
| lui $t, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b001111 |
????? |
5bit |
16bit |
|
LW -- Load word
| Description:
| A word is loaded into a register from the specified address.
|
| Operation:
| $t = MEM[$s + imm];
|
| Syntax:
| lw $t, imm($s)
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b100011 |
5bit |
5bit |
16bit |
|
MFHI -- Move from HI
| Description:
| The contents of register HI are moved to the specified register.
|
| Operation:
| $d = $HI;
|
| Syntax:
| mfhi $d
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5'h0 |
5'h0 |
5bit |
5'h0 |
6'b010000 |
|
MFLO -- Move from LO
| Description:
| The contents of register LO are moved to the specified register.
|
| Operation:
| $d = $LO;
|
| Syntax:
| mflo $d
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5'h0 |
5'h0 |
5bit |
5'h0 |
6'b010010 |
|
MTHI -- Move to HI
| Description:
| The contents of register $s are moved to $HI.
|
| Operation:
| $HI=$s;
|
| Syntax:
| mthi $s
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5'bit |
5'h0 |
5'h0 |
5'h0 |
6'b010001 |
|
MTLO -- Move to LO
| Description:
| The contents of register $s are moved to $HI.
|
| Operation:
| $LO=$s;
|
| Syntax:
| mtlo $s
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5'bit |
5'h0 |
5'h0 |
5'h0 |
6'b010011 |
|
MULT -- Multiply
| Description:
| Multiplies $s by $t and stores the result in $LO.
|
| Operation:
| $LO = $s * $t;
|
| Syntax:
| mult $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5'h0 |
5'h0 |
6'b011000 |
|
MULTU -- Multiply unsigned
| Description:
| Multiplies $s by $t and stores the result in $LO.
|
| Operation:
| $LO = $s * $t;
|
| Syntax:
| multu $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5'h0 |
5'h0 |
6'b011001 |
|
NOR -- Bitwise nor
| Description:
| Bitwise logical nors two registers and stores the result in a register
|
| Operation:
| $d = ~($s | $t);
|
| Syntax:
| nor $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5'h0 |
6'b100111 |
|
OR -- Bitwise or
| Description:
| Bitwise logical ors two registers and stores the result in a register
|
| Operation:
| $d = $s | $t;
|
| Syntax:
| or $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5'h0 |
6'b100101 |
|
ORI -- Bitwise or immediate
| Description:
| Bitwise ors a register and an immediate value and stores the result in a
register
|
| Operation:
| $t = $s | imm;
|
| Syntax:
| ori $t, $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b001101 |
5bit |
5bit |
16bit |
|
SB -- Store byte
| Description:
| The least significant byte of $t is stored at the specified address.
|
| Operation:
| MEM[$s + imm] = (0xff & $t);
|
| Syntax:
| sb $t, imm($s)
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b101000 |
5bit |
5bit |
16bit |
|
SH -- Store Half
| Description:
| The least significant half word of $t is stored at the specified address.
|
| Operation:
| MEM[$s + imm] = (0xffff & $t);
|
| Syntax:
| sh $t, imm($s)
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b101001 |
5bit |
5bit |
16bit |
|
SLL -- Shift left logical
| Description:
| Shifts a register value left by the shift amount listed in the instruction
and places the result in a third register. Zeroes are shifted in.
|
| Operation:
| $d = $t << h;
|
| Syntax:
| sll $d, $t, h
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
h |
6'b000000 |
|
SLLV -- Shift left logical variable
| Description:
| Shifts a register value left by the value in a second register and places
the result in a third register. Zeroes are shifted in.
|
| Operation:
| $d = $t << $s;
|
| Syntax:
| sllv $d, $t, $s
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
????? |
6'b000100 |
|
SLT -- Set on less than (signed)
| Description:
| If $s is less than $t, $d is set to one. It gets zero otherwise.
|
| Operation:
| if $s < $t $d = 1; else $d = 0;
|
| Syntax:
| slt $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5'h0 |
6'b101010 |
|
SLTI -- Set on less than immediate (signed)
| Description:
| If $s is less than immediate, $t is set to one. It gets zero otherwise.
|
| Operation:
| if $s < imm $t = 1; else $t = 0;
|
| Syntax:
| slti $t, $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b001010 |
5bit |
5bit |
16bit |
|
SLTIU -- Set on less than immediate unsigned
| Description:
| If $s is less than the unsigned immediate, $t is set to one. It gets zero
otherwise.
|
| Operation:
| if $s < imm $t = 1; else $t = 0;
|
| Syntax:
| sltiu $t, $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b001011 |
5bit |
5bit |
16bit |
|
SLTU -- Set on less than unsigned
| Description:
| If $s is less than $t, $d is set to one. It gets zero otherwise.
|
| Operation:
| if $s < $t $d = 1; else $d = 0;
|
| Syntax:
| sltu $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5'h0 |
6'b101011 |
|
SRA -- Shift right arithmetic
| Description:
| Shifts a register value right by the shift amount (shamt) and places the
value in the destination register. The sign bit is shifted in.
|
| Operation:
| $d = $t >> h;
|
| Syntax:
| sra $d, $t, h
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
h |
6'b000011 |
|
SRAV -- Shift right arithmatic variable
| Description:
| Shifts a register value right by the value in a second register and places
the result in a third register. the sign bit is shifterd in.
|
| Operation:
| $d = $t >> $s;
|
| Syntax:
| srav $d, $t, $s
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
????? |
6'b000111 |
|
SRL -- Shift right logical
| Description:
| Shifts a register value right by the shift amount (shamt) and places the
value in the destination register. Zeroes are shifted in.
|
| Operation:
| $d = $t >> h;
|
| Syntax:
| srl $d, $t, h
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
h |
6'b000010 |
|
SRLV -- Shift right logical variable
| Description:
| Shifts a register value right by the amount specified in $s and places the
value in the destination register. Zeroes are shifted in.
|
| Operation:
| $d = $t >> $s;
|
| Syntax:
| srlv $d, $t, $s
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5'h0 |
6'b000110 |
|
SUB -- Subtract
| Description:
| Subtracts two registers and stores the result in a register(Exception by Overflow)
|
| Operation:
| $d = $s - $t;
|
| Syntax:
| sub $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5'h0 |
6'b100010 |
|
SUBU -- Subtract unsigned
| Description:
| Subtracts two registers and stores the result in a register
|
| Operation:
| $d = $s - $t;
|
| Syntax:
| subu $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
5'h0 |
6'b100011 |
|
SW -- Store word
| Description:
| The contents of $t is stored at the specified address.
|
| Operation:
| MEM[$s + imm] = $t;
|
| Syntax:
| sw $t, imm($s)
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b101011 |
5bit |
5bit |
16bit |
|
SYSCALL -- System call
| Description:
| Generates a software interrupt.
|
| Operation:
|
|
| Syntax:
| syscall
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
????? |
????? |
????? |
????? |
6'b001100 |
|
XOR -- Bitwise exclusive or
| Description:
| Exclusive ors two registers and stores the result in a register
|
| Operation:
| $d = $s ^ $t;
|
| Syntax:
| xor $d, $s, $t
|
| Encoding:
|
| OPCODE |
Source |
Target |
Destination |
Shift |
Function |
| 6fb‚O‚O‚O‚O‚O‚O |
5bit |
5bit |
5bit |
????? |
6'b100110 |
|
XORI -- Bitwise exclusive or immediate
| Description:
| Bitwise exclusive ors a register and an immediate value and stores the
result in a register
|
| Operation:
| $t = $s ^ imm;
|
| Syntax:
| xori $t, $s, imm
|
| Encoding:
|
| OPCODE |
Source |
Target |
Immediate |
6'b001110 |
5bit |
5bit |
16bit |
|