8 F.A.Q.s

No	Question	Answer
1	First I want to run pure verilog rtl simulation, without any fpga stuff. I guess for this I need write a memory module and a register file module. Is that correct?	Correct. In addition to that, you need specific FIFO for uart write port. However,I have just written down new sources without FPGA library for the sake of convenience. They can be found in "rtl/generic" folder for that purpose. If you run on Veritak Simulator, "bench/verilog/generic_ram_rtl_trace_count.vtakprj" is good start point. It generates waveform at Section 5. At first, it is recommended to run Veritak Simulator for quick understanding of design structure. (2weeks are free as trial period.). After that, migration to another simulator will be easier.
2	I don't understand the purpose of tx/rx uart interface and how it functions. Is there a way to leave uart out. So before the program starts I will have the program and data transferred to the ram.	Tx/Rx uart is just used to verify implemented FPGA works propely. Several C programs are demonstrated with actual FPGA board. in Section 7. Without TX port (RX port in PC terminal), we can not see output of YACC. Without RX port(TX port in PC terminal), we ca not provide input to YACC as interactive calculator. That's why Tx/Rx uart is necessary. In RTL Simulation, Tx/Rx is very slow. So we use debug port in memory port. See Top of test bench and "print" in C. If you do not use UART, "leave it out with no input" is no problem. UART Read port generates interrupt to YACC per 1Byte receiving at 115.2Kbps, so it must be remained "high" or "low" if interrupt handling routine is not provided. Programs can be only done by using Memory Initialization File(HEX FILE).
3	. Have you implemented any interrupts?	Yes, very primitive interrupt is supported. UART RX port is only source of interrupt. (No interrupt controller in YACC).
4	Lastly for sw tools you mention that I have to download it from plasma website. Can I build the sw tools myself from the gcc/binutils distribution.	Yes, you can do it. I have successfully built cross-compiler on cygwin. You can also use newlib as mathematical floating libarary, such as sin/cos/exp/log.... Basically no hw bug is detected, but requires new "convert_mips2.exe" to generate hex file on gcc 3.4.4. See Section 7.3 use newlib
5	I am a Masters student in Computer Engineering.I am using YACC core designed by you in my research work. Documentation given by you is really very helpful, but i m not able to make out the exact use of UART.Can you please explain it in short.	I have added Section 7.1 and prepared Veritak Project for explaining it. Please See Section 7.1.
6	To start with ,I am trying to run some simple programs such as Ackermann func,fibonacci,etc...after compiling,mapping into memory and simulating, I am able to make out that its working correctly...but i m facing trouble in finding the memory locations or register locations where the final computed result is stored....is there anyway to know the exact location of computed result	For example,you can see following source at uart_echo_test.c in c_src/calculator unsigned char * read_ptr; char buffer[BUFFER_SIZE];// char result_buffer[8];//8+1 unsigned char sym; unsigned char* char_ptr; The address of these variables can be seen in "test.map" as follows. .sbss 0x00000b88 0x15 (.sbss) (.scommon) .scommon 0x00000b88 0x15 uart_echo_test.o 0x00000b88 result_buffer 0x00000b90 char_ptr 0x00000b94 buf 0x00000b98 read_ptr 0x00000b9c sym The addresses are all clear. Please note this is only available in static variables. Local variables are stacked and dumped, so its address is rather difficult to know directly. Further difficulty is to read the data in exact right timing.. In summary; 1)Define Static variables to store the final computed results. 2)After computation,damp the memory or write the data to debug-port for viewing the data. To move the data to another hardware, it it necessary to define new data port of hardware. In that case, UART write port can be referenced design as transfer-data port. I hope this will clear the question you raise.
7	I again had time to work with yacc this weekend and had couple of questions. I hope you can help me with those. I have a hardware block, with some registers and memory. I want to use yacc to program that block such that 0x0000 - 0x7fff addresses yacc regular dual port ram (actual ram size is just 16 Kbytes) 0x8000 - 0x8fff addresses the hardware block. I have implemented a mux that looks at Daddr to determine which address range to activate. I have discovered following int ptr; 1) ptr = (int ) 0x4000; ptr = 0xffff; // works 2) ptr = (int ) 0x8000; *ptr = 0xffff; // does not work MIPS assembler generates different for code segement two. And the generated code does not right address on the Daddr. I was wondering if you can give me some pointers on this.	It is rather difficult to implement new hardware block to YACC. In fact it takes 6hours for me to implement ! For the sake of convenience, I've just written added/changed hardware as an example of adding new hardware. The example is the same mapping of address space as you plan. Also I added small test bench for w/r the added h/w. The example is RTL only and not verified in FPGA. However I hope it is still useful for you. Here is design information. Test Bench: \count\count_tak_tariq.c with comple_tariq.bat Sources :\rtl\generic_tariq (All sources are here) Veritak Project File:generic_ram_rtl_tariq.vtakprj (See "\rtl\generic_tariq\veritak_command.txt" for compilation for another simulator See "\rtl\generic_tariq\define.h" for hardware mapping.) Here is a test result. Hello Tariq-san. 0x8010-0x8ffc W/R Test Starts! 00000000 00010001 00020002 00030003 ..... ....3f803f8 03f903f9 03fa03fa 03fb03fb Test Dump Done.Thanks a lot. This program is based on Steve Rhoards-san,author of plasma. Mult by 3 0000000003: three 0000000009: nine 0000000027: twenty seven 0000000081: eighty one 0000000243: two hundred forty three 0000000729: seven hundred twenty nine 0000002187: two thousand one hundred eighty seven 0000006561: six thousand five hundred sixty one 0000019683: nineteen thousand six hundred eighty three 0000059049: fifty nine thousand forty nine 0000177147: one hundred seventy seven thousand one hundred forty seven 0000531441: five hundred thirty one thousand four hundred forty one 0001594323: one million five hundred ninety four thousand three hundred twenty three 0004782969: four million seven hundred eighty two thousand nine hundred sixty nine 0014348907: fourteen million three hundred forty eight thousand nine hundred seven 0043046721: forty three million forty six thousand seven hundred twenty one 0129140163: one hundred twenty nine million one hundred forty thousand one hundred sixty three 0387420489: three hundred eighty seven million four hundred twenty thousand four hundred eighty nine 1162261467: one billion one hundred sixty two million two hundred sixty one thousand four hundred sixty seven
8	What I would like to do is; Read processed data from data memory of the processor to be sent to next core for further processing...	I can think of 2 ways. One is to use DMA Logic. This is rather difficult because full PORT of RAM has already used as program and data access. If 3 read port RAM is used, implementation will be easier but will require a lot of resources due to distributed RAM. So,my recommendation is another way, that is to use memory mapped IO like F.A.Q.7. I've just written C-test bench(bubble_tariq.c) using F.A.Q.7 hardware. ( See section.7.2 in detail) In this example, the calculation results(bubble sorted data) are transferred to another hardware register file(Memory mapped GPIO). Once transferred to the hardware, you can do any further processing by another hardware as you like, with capability of W/R from the point of YACC..
9	I was wondering if you had a zip file with the project file for the Xilinx Webpack development environment? I've tried downloading the YACC files from the opencores site but they seem incomplete.	See top of YACC page for download. Complete Spartan-3 starter Kit's project file (Interactive Calculator ) is provided in "syn\xilinx". s3_vsmpl.v is wrapper for the kit and synthesis top. s3_vsmpl.ucf is ucf file. Untitled.mcs is prom file. You will have calculator by hyperterminal at the baud rate of 57.6Kbps. Basically YACC itself has not been changed since opencores' release,synthesis was re-done by using the latest version of ISE 7.1SP3. It should be noted you need re-generation and re-synthesis of RAM for another program.
10	Couple of months ago I successfully interfaced Yacc with a dsp hardware blocked. I was able to program hardware blocks configuration registers and share its RAMS. Now I want to interface interrupts generated by the hardware block to YACC. The main idea is that when once the hardware block has finished its job it raises the interrupt. This interrupt causes the yacc to jump to a interrupt service routine which inspects some registers, sets up the next task and returns to normal execution. In yacc.v, I see there are you signal int_req and int_address which are being used when uart raises it interrupt. If you can provide a brief overview of these I might be able to add more interrupt sources to your scheme. Speciallt this statement " else if (DAddrD==16'h7ff8 & MWriteFF) int_address<=MemoryWData;" `ifdef RAM32K assign uart_write_req= DAddrD[15:0]==16'h07fff && MWriteFF ;//`UART_WRITE_PORT_ADDRESS ; always @ (posedge clock) begin if (sync_reset) int_address<=0; else if (DAddrD==16'h7ff8 & MWriteFF) int_address<=MemoryWData; end `endif //state machine //latch with one shot pulse //clear by clear_int always @(posedge clock) begin if (sync_reset) int_req <=1'b0; else if (clear_int) int_req <=1'b0;// assume one shot(1clk) pulse else if ( int_req_uport) int_req<=1'b1;// end Any help would be greatly appreciated.	Some consideration for implementing multiple nesting/priority is necessary. I will design example of interrupt controller in this week.