6 Post-Layout Gate Simulation
6.1 Spartan3 Gate Simulation

Memory Collision Errors are frequently reported as follows.

Since this messages are meaningless for YACC. I checked disable warning option in coregen generation. However situation was the same. There is no help for it , I changed primitive description temporally as follows.

parameter SIM_COLLISION_CHECK = "NONE";//All ORIG TAK Apr.12.2005



Note:
 SDF Error Messages are due to transitional state of simulator at initial power on sequence.




6.2 Stratix2

Run Test Bench at 165MHz.



6.3 Cyclone

Run test bench at 104MHz